Intel SPMD Program Compiler 1.9.1
Structure that collects optimization options. More...
Structure that collects optimization options.
This structure collects all of the options related to optimization of generated code.
On targets that don't have a masked store instruction but do have a blending instruction, by default, we simulate masked stores by loading the old value, blending, and storing the result. This can potentially be unsafe in multi-threaded code, in that it writes to locations that aren't supposed to be written to. Setting this value to true disables this work-around, and instead implements masked stores by 'scalarizing' them, so that we iterate over the ISIMD lanes and do a scalar write for the ones that are running.
Disables the 'coherent control flow' constructs in the language. (e.g. this causes "cif" statements to be demoted to "if" statements.) This is likely only useful for measuring the impact of coherent control flow.
Disables the optimization that detects when the execution mask is all on and emits code for gathers and scatters that doesn't loop over the SIMD lanes but just does the scalar loads and stores directly.
If enabled, disables the various optimizations that kick in when the execution mask can be determined to be "all on" at compile time.
Referenced by Function::emitCode(), DoStmt::EmitCode(), ForStmt::EmitCode(), IfStmt::emitMaskAllOn(), FunctionEmitContext::FunctionEmitContext(), lStoreAssignResult(), main(), Optimize(), IsCompileTimeConstantPass::runOnBasicBlock(), and FunctionEmitContext::StoreInst().
Disables the optimization that demotes masked stores to regular stores when the store is happening at the same control flow level where the variable was declared. This is likely only useful for measuring the impact of this optimization.
Disables uniform control flow optimizations (e.g. this changes an "if" statement with a uniform condition to have a varying condition). This is likely only useful for measuring the impact of uniform control flow.
Disables the optimizations that detect when arrays are being indexed with 'uniform' values and issue scalar loads/stores rather than gathers/scatters. This is likely only useful for measuring the impact of this optimization.
Indicates whether an vector load should be issued for masked loads on platforms that don't have a native masked vector load. (This may lead to accessing memory up to programCount-1 elements past the end of arrays, so is unsafe in general.)
Indicates if addressing math will be done with 32-bit math, even on 64-bit systems. (This is generally noticably more efficient, though at the cost of addressing >2GB).
Referenced by FunctionEmitContext::AddElementOffset(), FunctionEmitContext::addVaryingOffsetsIfNeeded(), FunctionEmitContext::applyVaryingGEP(), BinaryExpr::GetType(), SizeOfExpr::GetType(), NewExpr::GetValue(), lDeclareSizeAndPtrIntTypes(), lEmitBinaryPointerArith(), lGSToGSBaseOffsets(), main(), Target::SizeOf(), Target::StructOffset(), IndexExpr::TypeCheck(), and NewExpr::TypeCheck().
Always generate aligned vector load/store instructions; this implies a guarantee that all dynamic access through pointers that becomes a vector load/store will be a cache-aligned sequence of locations.
Referenced by Module::execPreprocessor(), FunctionEmitContext::FunctionEmitContext(), lEmitLoads(), lImproveMaskedLoad(), lImproveMaskedStore(), FunctionEmitContext::LoadInst(), main(), IntrinsicsOpt::runOnBasicBlock(), and FunctionEmitContext::StoreInst().
Optimization level. Currently, the only valid values are 0, indicating essentially no optimization, and 1, indicating as much optimization as possible.